This invention relates to semiconductor devices and more particularly to a structures and devices that enable a transistor to operate with a negative differential resistance mode. The present invention is applicable to a wide range of semiconductor integrated circuits, particularly for high-density memory and logic applications, as well as power management.
Devices that exhibit a negative differential resistance (NDR) characteristic, such that two stable voltage states exist for a given current level, have long been sought after in the history of semiconductor devices. When Nobel Prize winner Leo Esaki discovered the NDR characteristic in a resonant tunneling diode (RTD), the industry looked expectantly to the implementation of faster and more efficient circuits using these devices. NDR based devices and principles are discussed in a number of references, including the following that are hereby incorporated by reference and identified by bracketed numbers [ ] where appropriate below:
[1] P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun and G. I. Haddad, xe2x80x9cDigital Circuit Applications of Resonant Tunneling Devices,xe2x80x9d Proceedings of the IEEE, Vol. 86, No. 4, pp. 664-686, 1998.
[2] W. Takao, U.S. Pat. No. 5,773,996, xe2x80x9cMultiple-valued logic circuitxe2x80x9d (issued Jun. 30, 1998).
[3] Y. Nakasha and Y. Watanabe, U.S. Pat. No. 5,390,145, xe2x80x9cResonance tunnel diode memoryxe2x80x9d (issued Feb. 14, 1995).
[4] J. P. A. Van Der Wagt, xe2x80x9cTunneling-Based SRAM,xe2x80x9d Proceedings of the IEEE, Vol. 87, No. 4, pp. 571-595, 1999.
[5] R. H. Mathews, J. P. Sage, T. C. L. G. Sollner, S. D. Calawa, C.-L. Chen, L. J. Mahoney, P. A. Maki and K. M Molvar, xe2x80x9cA New RTD-FET Logic Family,xe2x80x9d Proceedings of the IEEE, Vol. 87, No. 4, pp. 596-605, 1999.
[6] H. J. De Los Santos, U.S. Pat. No. 5,883,549, xe2x80x9cBipolar junction transistor (BJT)xe2x80x94resonant tunneling diode (RTD) oscillator circuit and method (issued Mar. 16, 1999).
[7] S. L. Rommel, T. E. Dillon, M. W. Dashiell, H. Feng, J. Kolodzey, P. R. Berger, P. E. Thompson, K. D. Hobart, R. Lake, A. C. Seabaugh, G. Klimeck and D. K. Blanks, xe2x80x9cRoom temperature operation of epitaxially grown Si/Si0.5Ge0.5/Si resonant interband tunneling diodes,xe2x80x9d Applied Physics Letters, Vol. 73, No. 15, pp. 2191-2193, 1998.
[8] S. J. Koester, K. Ismail, K. Y. Lee and J. 0. Chu, xe2x80x9cNegative differential conductance in lateral double-barrier transistors fabricated in strained Si quantum wells,xe2x80x9d Applied Physics Letters, Vol. 70, No. 18, pp. 2422-2424, 1997.
[9] G. I. Haddad, U. K. Reddy, J. P. Sun and R. K. Mains, xe2x80x9cThe bound-state resonant tunneling transistor (BSRTT): Fabrication, d.c. I-V characteristics, and high-frequency properties,xe2x80x9d Superlattices and Microstructures, Vol. 7, No. 4, p. 369, 1990.
[10] Kulkarni et. al., U.S. Pat. No. 5,903,170, xe2x80x9cDigital Logic Design Using Negative Differential Resistance Diodes and Field-Effect Transistors (issued May 11, 1999).
A wide range of circuit applications for NDR devices are proposed in the above references, including multi-valued logic circuits [1,2], static memory (SRAM) cells [3,4], latches [5], and oscillators [6]. To date, technological obstacles have hindered the widespread use of RTD devices in conventional silicon-based integrated circuits (ICs), however.
The most significant obstacle to large-scale commercialization has been the technological challenge of integrating high-performance NDR devices into a conventional IC fabrication process. The majority of RTD-based circuits require the use of transistors, so the monolithic integration of NDR devices with predominant complementary metal-oxide-semiconductor (CMOS) transistors is the ultimate goal for boosting circuit functionality and/or speed. Clearly, the development of a CMOS-compatible NDR device technology would constitute a break-through advancement in silicon-based IC technology. The integration of NDR devices with CMOS devices would provide a number of benefits including at least the following for logic and memory circuits:
1) reduced circuit complexity for implementing a given function;
2) lower-power operation; and
3) higher-speed operation.
Significant manufacturing cost savings could be achieved concomitantly, because more chips could be fabricated on a single silicon wafer without a significant increase in wafer-processing cost. Furthermore, a CMOS compatible NDR device could also be greatly utilized in power management circuitry for ICs, which is an area of growing importance due to the proliferation of portable electronic devices (PDAs, cell phones, etc.).
A tremendous amount of effort has been expended over the past several decades to research and develop silicon-based NDR devices in order to achieve compatibility with mainstream CMOS technology, because of the promise such devices hold for increasing IC performance and functionality. Efforts thus far have only yielded quantum-mechanical-tunneling-based devices that require either prohibitively expensive process technology or extremely low operating temperatures which are impractical for high-volume applications. One such example in the prior art requires deposition of alternating layers of silicon and silicon-germanium alloy materials using molecular beam epitaxy (MBE) to achieve monolayer precision to fabricate the NDR device [7]. MBE is an expensive process which cannot be practically employed for high-volume production of semiconductor devices. Another example in the prior art requires the operation of a device at extremely low temperatures (1.4 K) in order to achieve significant NDR characteristics [8]. This is impractical to implement for high-volume consumer electronics applications.
A further drawback of the tunnel diode is that it is inherently a two-terminal device. Three (or more) terminal devices are preferred as switching devices, because they allow for the conductivity between two terminals to be controlled by a voltage or current applied to a third terminal, an attractive feature for circuit design as it allows an extra degree of freedom and control in circuit designs. Three-terminal quantum devices which exhibit NDR characteristics such as the resonant tunneling transistor (RTT) [9] have been demonstrated; the performance of these devices has also been limited due to difficulties in fabrication, however. Some bipolar devices (such as SCRs) also can exhibit an NDR effect, but this is limited to embodiments where the effect is achieved with two different current levels. In other words, the I-V curve of this type of device is not extremely useful because it does not have two stable voltage states for a given current.
Accordingly, there exists a significant need for a new three-terminal NDR device which can be easily and reliably implemented in a conventional CMOS technology. In addition, it is further desirable that such a three-terminal device can be operated at room temperature.
One useful observation made by the inventors concerning an ideal NDR device is to notice that its I-V curve looks essentially like that of a non-volatile memory cell that has a dynamic and reversible threshold voltage. The inventors thus noted that if a non-volatile memory could be controlled in this fashion, it might be possible to achieve an NDR effect. To date, however, the inventors are unaware of anyone succeeding with or even attempting such an approach. For example, in a prior art device described in U.S. Pat. No. 5,633,178, and incorporated by reference herein, a type of volatile memory device is depicted, in which electrons are stored in charge traps near a substrate/dielectric layer interface. Notably, this reference discusses the filling and emptying of the traps through programming operations (to store a 0 or 1), but does not identify any implementation or variation that is suitable for an NDR application, or which even suggests that it is capable of dynamic or quickly reversible threshold voltage operation. Similar prior art references also identify the use of charge traps for non-volatile memories, but none again apparently recognize the potential use for such structures in an NDR context. See, e.g., U.S. Pat. Nos. 4,047,974; 4,143,393; 5,162,880 and 5,357,134 incorporated by reference herein.
An object of the present invention is to provide a new type of semiconductor device, which like the tunnel diode, exhibits a negative differential resistance (NDR) characteristic that can be utilized to dramatically improve the performance and functionality of integrated circuits;
Another object of the present invention is to provide a new NDR device in which band-to-band tunneling is not the sole physical mechanism responsible for the negative differential resistance characteristic;
Another object of the present invention is to provide a new device in which charge trapping can be used for achieving a negative differential resistance characteristic;
Yet another object of the present invention is to provide a new NDR device with full transistor features (i.e., a three-terminal device), where the conductivity between two terminals is controlled by a voltage or current applied to the third terminal;
Yet another object of the present invention is to provide a new NDR device which can be fabricated with a process that is fully compatible with conventional CMOS process technology;
Yet another object of the present invention is to provide a new NDR device whose lateral dimensions can scale in proportion with the scaling of CMOS devices;
Yet another object of the present invention is provide a new NDR device where the voltage corresponding to the onset of negative differential resistance is fully tunable;
Yet another object of the present invention is to provide a new device where the peak current as well as the negative differential resistance between two terminals can be tailored by adjusting the voltage applied to a third terminal;
Finally, another object of the present invention is to provide a device that will be useful for power management applications in portable electronic devices, including as a voltage regulator, an overcurrent protection device, etc.
These and other objects are achieved by the present invention that discloses a new NDR transistor that can be implemented using conventional integrated-circuit process technology. The new device offers significant advantages over prior art: an electronically tunable NDR; extremely high peak-to-valley current ratio (greater than 1000 for room-temperature operation); compatibility with conventional CMOS process technology; and scalability to future generations of CMOS integrated-circuit technology.
A first aspect of the invention concerns a semiconductor transistor device that achieves a negative differential resistance mode by using a dynamically variable and reversible threshold voltage. The threshold voltage can be dynamically controlled using a conventional gate control signal. Unlike prior art devices, the negative differential resistance is based on temporary charge trapping/detrapping mechanism, and not on a band-to-band tunneling mechanism.
Another aspect of the invention pertains to a semiconductor transistor device which has three control terminals, and is operable with a negative differential resistance mode by applying a bias signal across two of the terminals to set up a current path between the two terminals, and a control signal to a separate third terminal for controlling conduction in the current path by controlling a density of charge carriers available in the current path.
Another aspect of the invention concerns a single charge carrier semiconductor device which is operable with a negative differential resistance mode as noted above with two stable voltage states, and is fabricated using only complementary metal oxide semiconductor (CMOS) processing.
A further aspect of the invention pertains to a dielectric trapping layer located proximate to a transistor channel. The transistor channel is capable of carrying a current that varies from a first current value associated with a conducting condition for the transistor channel, to a second current value associated with a non-conducting condition for the transistor channel channel, the second current value being substantially less than the first current value. A plurality of carrier trapping sites within the dielectric layer are configured for trapping carriers that are electrically biased by an electrical control field to move from the channel into the dielectric layer. A negative differential resistance mode can be caused in the channel by rapid trapping and de-trapping of electrons to and from the charge trapping sites.
The trapping sites have a concentration and arrangement within the dielectric layer so that the current in the transistor channel can be varied between the first current value and the second current value by the action of the trapping sites adjusting the current in accordance with a value of the electrical control field, and such that the transistor channel exhibits negative differential resistance. This is due to the fact that a field generated by the carriers stored in the trapping layer can be adjusted to be sufficiently large so as to cause the channel to be depleted of carriers, thus reducing the current in the channel even as the channel bias voltage is increased, and dynamically increasing a threshold voltage of an associated FET.
Other more detailed aspects of the trapping layer and trapping sites include the fact that the trapping sites are located very close (within 1.5 nm preferably) to the channel/trapping layer interface. Furthermore, the trapping and detrapping time of the electrical charges can be controlled through the placement and concentration of the trapping sites. In this fashion, a device can exhibit anything from very short/temporary storage times to very long storage times so that a useful substitute can be realized for a non-volatile floating gate type structure. This type of embedded, spatially distributed electrode of the present invention can exhibit substantial operating advantages over conventional single layer, continuous type electrodes commonly used in non-volatile memories.
Another aspect of the invention relates to the fact that the trapping layer is used in connection with a FET so that in a first operating region for the FET the source-drain current has a value that increases as the lateral electrical field between the source and drain increases, and in a second operating region for the semiconductor device the source-drain current has a value that decreases as the electrical field increases. Accordingly the drain region and the gate are controlled so that the device constitutes a three terminal device that can be operated in a range that exhibits negative differential resistance, because the charge trapping sites in the gate dielectric serve to trap electrons, causing the FET threshold voltage to increase dynamically, thereby reducing an output current of the FET as a drain-to-source voltage difference is increased. The trapping and de-trapping actions are also controlled so that they do not occur primarily near a drain junction of the FET. Other more detailed features of this aspect of the invention include the fact that the drain dopant concentration profile is tailored to minimize impact ionization current between the drain region and the channel region as well as to minimize junction capacitance between the drain region and the semiconductor substrate.
Other more detailed features of this aspect of the invention include the fact that the trapping layer is formed as an integral part of a gate dielectric for the FET which includes one or more of the following materials: silicon-dioxide, silicon-nitride, and/or silicon-oxynitride, and/or a high-permittivity layer with a relative permittivity greater than approximately eight (8). Furthermore, this gate dielectric has a thickness adapted to minimize loss of trapped charge due to quantum-mechanical tunneling. When the gate dielectric is silicon-dioxide it can be formed either entirely or partially by thermal oxidation of heavily doped ( greater than 1018 cmxe2x88x923) p-type silicon. The charge trapping sites thus consist of defects within the silicon-dioxide formed by thermal oxidation of the doped p-type silicon. Alternatively, the charge trapping sites can consist of islands of metal or semiconductor material, or even a floating gate embedded in the gate dielectric.
In other variations, the trapping layer/gate dielectric consists of a plurality of dielectric layers. In such embodiments, the charge trapping sites can consist of defects located near an interface between adjacent layers of the gate dielectric.
Another aspect of the invention pertains to the fact that the channel can be subjected to an electrical field having a first field component along the surface resulting from a bias voltage applied to the source and drain regions, and a second field component substantially perpendicular to the surface resulting from a control voltage applied to the control gate. These field components control how carriers in the channel acquire sufficient energy to overcome an interface barrier between the channel and the trapping layer, and how quickly they are trapped and detrapped.
Other more detailed aspects of the invention pertaining to the channel characteristics include the fact that the energetic (xe2x80x9chotxe2x80x9d) carriers are generated (and thus trapped) substantially uniformly throughout a length of the channel region, instead of being concentrated at a junction interface as occurs in the prior art. The channel is also heavily p-type doped, and has a dopant concentration that peaks near the semiconductor surface, to enhance the generation of hot electrons. Furthermore, it can be offset from the source and drain regions to minimize junction capacitance.
Other aspects of the present invention relate to methods of operating the devices described above.
Finally, other aspects of the present invention relate to methods of making the structures and devices above. These include manufacturing processes which are compatible with conventional CMOS techniques used in commercial semiconductor facilities, thus providing a substantial advantage over the prior art. An additional benefit lies in the fact that the onset point for the negative differential resistance mode can be adjusted during the making of the device.